`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:36:18 06/30/2015 
// Design Name: 
// Module Name:    Etapa2 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module Etapa2(
	input [31:0] instruccion,
	input [31:0] E1Adder,
	input [4:0] DestinoReg,
	input [31:0] WriteData,
	input RegWrite,
	input clk,
	output RegDst, 
	output RegWriteO,
	output ALUSrc, 
	output PCSrc,
	output MemRead,
	output [3:0] MemWrite,
	output MemToReg,
	output [1:0] ALUOp, 
	output jmp, 
	output [2:0] LoadOp, 
	output [1:0] StoreOp, 
	output [2:0] InmCtrl,
	output [31:0] E2Adder,
	output [31:0] ReadData1,
	output [31:0] ReadData2,
	output [31:0] ExtSig,
	output [4:0] RT,
	output [4:0] RD,
	output [4:0] RS,
	output [31:0] jmpAddr
	//output [4:0] ShiftAmount
    );

assign E2Adder = E1Adder;
assign RT = instruccion[20:16];
assign RS = instruccion[25:21];
assign RD = instruccion[15:11];
//assign ShiftAmout = instruccion[10:6];
assign jmpAddr = {E1Adder[31:28],salidaS[27:0]};
wire [31:0] salidaS;

MemoriaRegistros MemRegs(
.readPos1(instruccion[25:21]),
.readPos2(instruccion[20:16]),
.writePos(DestinoReg),
.writeData(WriteData),
.readData1(ReadData1),
.readData2(ReadData2),
.clk(clk),
.RegWrite(RegWrite));

SignExtend Extension(
.in(instruccion[15:0]),
.out(ExtSig)
);

MainControl Control(
.op(instruccion[31:26]),
.RegDst(RegDst), 
.RegWrite(RegWriteO),
.ALUSrc(ALUSrc), 
.PCSrc(PCSrc),
.MemRead(MemRead),
.MemWrite(MemWrite),
.MemToReg(MemToReg),
.ALUOp(ALUOp), 
.jmp(jmp), 
.LoadOp(LoadOp), 
.StoreOp(StoreOp), 
.InmCtrl(InmCtrl)
);

ShiftLeft2 shifter(
.in(instruccion),
.out(salidaS));
endmodule
